Performance Metric Evaluation of Error-Tolerant Adders for 2D Image Blending

The hardware implementation of error-tolerant adders using the paradigm approximate computing has considerably influenced performance metrics, especially in applications that can compromise accuracy. foundation for processing is inclusion errors design to enhance effectiveness and reduce complexity. This work presents three base novel concept error tolerance digital VLSI design. research extended construct nine variants power delay-efficient 16 32-bit carry select (CSLA). To attain optimization delay, conventional CSLA refined by substituting ripple (RCA) with newly proposed selector unit minimize switching activity. includes power, area, delay estimates from synthesis gpdk-90 nm gpdk-45 standard cell libraries. exhibit reduced dissipation, product (PDP), energy (EDP), area (ADP) compared existing adders. adder used an image blending application. There a significant improvement peak-signal-to-noise ratio (PSNR) blended designs.